Methods for producing near zero channel length field drift LDMOS

Patent metadata

Field	Value
Publication number	US-9105657-B2
Application number	US-201314071344-A
Country	US
Kind code	B2
Filing date	Nov 4, 2013
Priority date	Feb 11, 2011
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space adjacent the drain, is avoided by providing a lightly doped region of a first conductivity type (CT) separating the first CT drift space from an opposite CT WELL region in which the first CT source is located, and a further region of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region under an edge of the gate located near a boundary of the WELL region into the lightly doped region, and a shallow still further region of the first CT Ohmically coupled to the source and ending near the gate edge whereby the effective channel length in the further region is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties.

First claim

What is claimed is:

1. A method for forming a field LDMOS device, comprising:
providing a semiconductor (SC) body with a first conductivity type (CT) semiconductor (SC) region of a first thickness extending therein from a first surface thereof;
forming a WELL region of a second, opposite, opposite conductivity type (CT) in the semiconductor (SC) region;
forming a first conductivity type (CT) drift space laterally spaced from the WELL region by a part of the first semiconductor…

Assignees

• Yang Hongning
• Lin Xin
• Zuo Jiang-Kai
• Freescale Semiconductor Inc

Inventors

• Yang Hongning
• Lin Xin
• Zuo Jiang-Kai

Classifications

• H10P30/222

  Electricity · mapped topic

• H10D62/371

  Electricity · mapped topic

• H10D62/157

  Electricity · mapped topic

• H10D62/116

  Electricity · mapped topic

• H10D62/393

  Electricity · mapped topic