Capacitor and semiconductor device including the same
US-2024387608-A1 · Nov 21, 2024 · US
Methods for reproducible flash layer deposition
US9105646B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105646-B2 |
| Application number | US-201213731548-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 31, 2012 |
| Priority date | Dec 31, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.
First claim
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What is claimed: 1. A semiconductor layer stack comprising: a first electrode layer formed above a substrate; a dielectric layer formed above the first electrode layer; a second electrode layer formed above the dielectric layer; at least one of a flash layer between the first electrode layer and the dielectric layer, or a capping layer between the dielectric layer and the second electrode layer; wherein the at least one of the flash layer or the capping layer is formed by…
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- What does patent US9105646B2 cover?
- A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be f…
- Who is the assignee on this patent?
- Intermolecular Inc, Elpida Memory Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D1/684. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).