Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Bit cell with double patterned metal layer structures
US9105643B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105643-B2 |
| Application number | US-201414337596-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 22, 2014 |
| Priority date | Sep 14, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.
First claim
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What is claimed is: 1. A device comprising: at least one word line structure having a first tip edge and a first side edge; at least one ground line structure having a second tip edge and a second side edge; at least one power line structure; and at least one bit line structure proximate the at least one word line structure, the at least one ground line structure, and the at least one power line structure; the at least one word line structure, the at least one ground line…
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- What does patent US9105643B2 cover?
- An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the …
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W70/65. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).