Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure
US-9202813-B2 · Dec 1, 2015 · US
Semiconductor device
US9105618B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105618-B2 |
| Application number | US-201414166093-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 28, 2014 |
| Priority date | Sep 17, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device according to an embodiment includes a gate wire including a laminated film in which a polysilicon film, a barrier conductive film, and a metal film are laminated in this order; a first contact plug/upper layer wire arranged above the source or the drain; a second upper layer wire arranged above an element isolation region; a second contact plug arranged apart from the second upper layer wire and connecting the metal film and the polysilicon film above a channel region; and a third contact plug formed apart from the polysilicon film in the element isolation region and connecting the second upper layer wire and the metal film. The second contact plug includes a barrier metal in contact with the polysilicon film and the barrier conductive film is made of WN, TaN, or Ta and the barrier metal is made of Ti or TiN.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a gate wire extending from a channel region into an element isolation region and including a laminated film in which a polysilicon film, a barrier conductive film, and a metal film are laminated in this order from a lower layer side; a first contact plug connected to a source or a drain adjacent to the channel region; a first upper layer wire arranged above the source or the drain and connected to the first contact plug…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10D64/664Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L29/4941Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105618B2 cover?
- A semiconductor device according to an embodiment includes a gate wire including a laminated film in which a polysilicon film, a barrier conductive film, and a metal film are laminated in this order; a first contact plug/upper layer wire arranged above the source or the drain; a second upper layer wire arranged above an element isolation region; a second contact plug arranged apart from the sec…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D64/664. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).