Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Semiconductor structure having material layers which are level with each other and manufacturing method thereof
US9105590B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105590-B2 |
| Application number | US-201113206523-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 10, 2011 |
| Priority date | Aug 10, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a substrate having at least a trench region, wherein from top view of the substrate, the trench region includes two separated first regions, and a second region between and adjacent to the two first regions; a first material layer disposed on the substrate outside the trench region; a second material layer disposed in the second region; and a third material layer only disposed in the first regions, wherein a top s…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P50/71Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9105590B2 cover?
- A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is dispos…
- Who is the assignee on this patent?
- Chen Tong-Yu, United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P50/71. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).