Method for manufacturing pillar-shaped semiconductor device
US-9224834-B1 · Dec 29, 2015 · US
Interface engineering to optimize metal-III-V contacts
US9105571B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105571-B2 |
| Application number | US-201213368750-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 8, 2012 |
| Priority date | Feb 8, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a self-aligned contact to a III-V material, the method comprising the steps of: implanting one or more dopants into the III-V material to selectively form one or more separate and distinct implanted regions in the III-V material; after the implanted regions are formed, depositing at least one metal on a surface of the III-V material; reacting the at least one metal with an upper portion of the III-V material to form a metal-III-V…
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Electricity · mapped topic
Electricity · mapped topic
- H10P32/14Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105571B2 cover?
- Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-ali…
- Who is the assignee on this patent?
- Lavoie Christian, Rana Uzma, Sadana Devendra K, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10P32/14. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).