Making ESD diode with P-S/D overlying N-well and P-EPI portion

Patent metadata

Field	Value
Publication number	US-9105567-B2
Application number	US-201313886466-A
Country	US
Kind code	B2
Filing date	May 3, 2013
Priority date	Jun 4, 2010
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.

First claim

What is claimed is:

1. A process of making an electrostatic discharge diode in an integrated circuit, comprising:
A. forming an N-type buried layer in a semiconductor substrate;
B. forming a deep N-type implant region in the substrate extending down from a first level of the substrate to the N-type buried layer;
C. forming a first N well region in the substrate and extending down to the N-type buried layer;
D. forming a second N well region in the substrate and extending do…

Assignees

• Texas Instruments Inc

Inventors

• Chuang Ming-Yeh

Classifications

• H10P30/20

  Electricity · mapped topic

• H10P32/00 Primary

  Electricity · mapped topic

• H10D89/611 Primary

  Electricity · mapped topic

• H10D62/126

  Electricity · mapped topic

• H10D62/105

  Electricity · mapped topic