Nitride semiconductor device

US9105565B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105565-B2
Application numberUS-201313792426-A
CountryUS
Kind codeB2
Filing dateMar 11, 2013
Priority dateMar 26, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to one embodiment, a nitride semiconductor device includes semiconductor stacked layers provided on a substrate and including a nitride semiconductor; a source electrode and a drain electrode provided on the layers and being in contact with the layers; and a gate electrode provided on the layers and provided between the source electrode and the drain electrode. The layers have a first barrier layer, a second barrier layer, and a carrier running layer interposed between the first barrier layer and the second barrier layer. The second barrier layer and the carrier running layer are removed in a region in which the source electrode on the layers is provided. A part of the source electrode is in contact with the first barrier layer. And another part of the source electrode other than the part of the source electrode is in contact with the second barrier layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A nitride semiconductor device comprising: a substrate; semiconductor stacked layers disposed on the substrate, comprising a nitride semiconductor; a source electrode and a drain electrode disposed on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode disposed on the semiconductor stacked layers and between the source electrode and the drain electrode, wherein: the semiconductor stacked layer…

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What does patent US9105565B2 cover?
According to one embodiment, a nitride semiconductor device includes semiconductor stacked layers provided on a substrate and including a nitride semiconductor; a source electrode and a drain electrode provided on the layers and being in contact with the layers; and a gate electrode provided on the layers and provided between the source electrode and the drain electrode. The layers have a first…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10D62/8503. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).