Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Integrated circuit package and packaging methods
US9105562B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105562-B2 |
| Application number | US-201113326527-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 15, 2011 |
| Priority date | May 9, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit packaging method comprising: fabricating a package module from successive build-up layers which define circuit interconnections; forming a cavity on a top-side of the package module; attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact; disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the c…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105562B2 cover?
- An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward co…
- Who is the assignee on this patent?
- Meyer-Berg Georg, Daeche Frank, Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification H10W70/09. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).