Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Schottky-barrier device with locally planarized surface and related semiconductor product
US9105557B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105557-B2 |
| Application number | US-201313920933-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 18, 2013 |
| Priority date | Jun 27, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
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The present disclosure is related to alleviation of at least some of the drawbacks of the previously known implementations and to provide an improved alternative. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a planarized surface.
First claim
Opening claim text (preview).
What is claimed is: 1. A power rectifier device, comprising: a drift layer including silicon carbide; and a Schottky electrode disposed on the drift layer, the Schottky electrode and a surface of the drift layer providing a Schottky contact, the drift layer having a planarized surface such that a depth of each of a plurality of pits of the surface of the drift layer is less than approximately D max E b /F a , where E b is a metal-semiconductor barrier height and F a is an av…
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Electricity · mapped topic
- H10P50/00Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105557B2 cover?
- The present disclosure is related to alleviation of at least some of the drawbacks of the previously known implementations and to provide an improved alternative. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a planarized surface.
- Who is the assignee on this patent?
- Fairchild Semiconductor
- What technology area does this patent fall under?
- Primary CPC classification H10P50/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).