High productivity combinatorial material screening for metal oxide films

Patent metadata

Field	Value
Publication number	US-9105526-B2
Application number	US-201314134571-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Dec 19, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnO x , ZnSnO x , ZnInO x , or ZnGaO x ) deposition, metal-based semiconductor (e.g. ZnO x , ZnSnO x , ZnInO x , or ZnGaO x ) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

First claim

What is claimed is:

1. A method for forming a plurality of thin film transistors on a substrate in a combinatorial manner, the method comprising:
providing the substrate, wherein the substrate comprises a plurality of site-isolated regions, and wherein each site-isolate region further comprises one or more gate electrodes formed therein;
depositing a gate dielectric layer above a surface of each site-isolated region;
patterning the gate dielectric layer deposited above the sur…

Assignees

• Intermolecular Inc

Inventors

• Le Minh Huu
• Lee Sang
• Van Duren Jeroen

Classifications

• H10P74/207

  Electricity · mapped topic

• H10P14/3426

  Electricity · mapped topic

• H10P74/23

  Electricity · mapped topic

• H10P14/3434 Primary

  Electricity · mapped topic

• H10D86/423

  Electricity · mapped topic