Pulse output circuit, shift register and display device

Patent metadata

Field	Value
Publication number	US-9105520-B2
Application number	US-201414332468-A
Country	US
Kind code	B2
Filing date	Jul 16, 2014
Priority date	May 11, 2001
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

First claim

What is claimed is:

1. A semiconductor device comprising:
a shift register comprising a plurality of pulse output circuits,
wherein at least one of the plurality of pulse output circuits comprises:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor; and
an eighth transistor,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor…

Assignees

• Semiconductor Energy Lab

Inventors

• Azami Munehiro
• Nagao Shou
• Tanada Yoshifumi

Classifications

• G09G3/3688

  Physics · mapped topic

• G11C19/28 Primary

  Physics · mapped topic

• G09G2310/0286

  Physics · mapped topic

• G09G2330/021

  Physics · mapped topic

• G02F1/13306

  Physics · mapped topic