Integrated Assemblies Having Conductive Posts Extending Through Stacks of Alternating Materials
US-2024237336-A9 · Jul 11, 2024 · US
3D non-volatile memory device, memory system including the same, and method of manufacturing the same
US9105515B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105515-B2 |
| Application number | US-201414559594-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 3, 2014 |
| Priority date | Dec 20, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a 3D non-volatile memory device, comprising: alternately depositing first material layers and second material layers on a substrate; forming vertical channel layers passing through the first material layers and the second material layers; forming a slit between the vertical channel layers by etching the first material layers and the second material layers; forming trenches by removing the second material layers exposed through…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/0413Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9105515B2 cover?
- A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal pa…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0413. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).