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Transistor of semiconductor device and method for fabricating the same
US9105508B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105508-B2 |
| Application number | US-201213487482-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 4, 2012 |
| Priority date | Jun 28, 2007 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
Official abstract text for this publication.
Provided is a transistor of a semiconductor device and a method for fabricating the same. A transistor of a semiconductor device may include: a semiconductor substrate having an active region defined by an isolation layer; a recess trench formed in the active region and disposed to cross the semiconductor substrate in one direction; and a gate line formed in a straight line pattern, overlapping the recess trench and disposed to cross the recess trench at approximately right angles.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a transistor of a semiconductor device, the method comprising: forming isolation layers to define at least a first active region, a second active region, a third active region, and a fourth active region in a semiconductor substrate, wherein the first and second active regions are parallelized in a Y-axis direction of the semiconductor substrate, the first and third active regions are parallelized in an X-axis direction of the semico…
Assignees
Inventors
Classifications
- H10D64/519Primary
Electricity · mapped topic
Electricity · mapped topic
- H01L27/10894Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105508B2 cover?
- Provided is a transistor of a semiconductor device and a method for fabricating the same. A transistor of a semiconductor device may include: a semiconductor substrate having an active region defined by an isolation layer; a recess trench formed in the active region and disposed to cross the semiconductor substrate in one direction; and a gate line formed in a straight line pattern, overlapping…
- Who is the assignee on this patent?
- Kang Chun Soo, Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D64/519. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).