Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
Gate strain induced work function engineering
US9105498B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105498-B2 |
| Application number | US-201213409630-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 1, 2012 |
| Priority date | Mar 1, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor structure comprising: forming a stack of a gate dielectric layer and a workfunction material layer over a first semiconductor material portion and a second semiconductor material portion; forming a first gate conductor material layer applying a first stress to a first workfunction material portion of said workfunction material layer that is present over said first semiconductor material portion, wherein said first workfu…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105498B2 cover?
- A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconducto…
- Who is the assignee on this patent?
- Bajaj Mohit, Murali Kota V R M, Nayak Rahul, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/85. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).