Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
US9105480B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105480-B2 |
| Application number | US-201313829078-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 14, 2013 |
| Priority date | Mar 14, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors.
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What is claimed is: 1. A method of fabricating a graphene nanoribbon array, the method comprising: forming a graphoepitaxy channel over a graphene substrate, the channel comprising side walls and a floor; depositing a layer of a surface-modifying copolymer on the side walls and the floor of the channel; depositing a block copolymer in the channel and subjecting the block copolymer to conditions under which spatial confinement of the block copolymer by the channel induces the b…
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