Electronic circuit
US-11916061-B2 · Feb 27, 2024 · US
ESD protection structure and ESD protection circuit
US9105477B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105477-B2 |
| Application number | US-201414227500-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 27, 2014 |
| Priority date | Mar 28, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference.
First claim
Opening claim text (preview).
What is claimed is: 1. An electrostatic discharge (ESD) protection structure comprising: a semiconductor substrate including a first N-type well region and a first P-type well region, the first N-type well region including a first region and a second region, and the first P-type well region including a third region and a fourth region; a PMOS transistor located in the first region of the first N-type well region, the PMOS transistor including a gate located on the first N-type w…
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Classifications
- H10D89/815Primary
Electricity · mapped topic
- H01L27/0277Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105477B2 cover?
- An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is locate…
- Who is the assignee on this patent?
- Semiconductor Mfg Int Shanghai
- What technology area does this patent fall under?
- Primary CPC classification H10D89/815. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).