Two-tier defect scan management
US-2024402922-A1 · Dec 5, 2024 · US
US9105356B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105356-B2 |
| Application number | US-201314016187-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 2, 2013 |
| Priority date | Dec 25, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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A semiconductor device includes a first transistor connected to an internal voltage terminal and a first node at which a first resistance unit is connected. The first resistance unit includes a resistor connected between the first node and a node from which a monitoring voltage is provided for controlling the first transistor. This resistance unit also includes a first resistance adjustment unit connected in parallel with the first resistor. Also included is a second resistance unit having a third resistor connected between the monitor node and a second node which is connected to a ground potential and a second resistance adjustment unit connected in parallel with the third resistor. A comparator comparing the monitor node voltage to a reference is provided with an output terminal connected the first transistor. Also included is a control circuit to control the resistance adjustment units.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a first transistor having a first end connected to an internal voltage terminal and a second end connected to a first node; a first resistance unit including: a first resistor connected between the first node and a monitor node, and a first resistance adjustment unit connected in parallel with the first resistor, the first resistance adjustment unit including a second resistor and a first switch connected in series;…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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