Memory cell array operated with multiple operation voltage

Patent metadata

Field	Value
Publication number	US-9105355-B2
Application number	US-201313935487-A
Country	US
Kind code	B2
Filing date	Jul 4, 2013
Priority date	Jul 4, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.

First claim

What is claimed is:

1. A memory cell array, comprising:
a bit line;
a complementary bit line;
a first operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, configured to provide a first operation voltage;
a second operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, configured to provide a second operation voltage;
a first memory cell, electrically coupled to the bit line and…

Assignees

• United Microelectronics Corp

Inventors

• Chen Hsin-Wen

Classifications

• G11C11/413

  Physics · mapped topic

• G11C7/12

  Physics · mapped topic

• G11C11/417 Primary

  Physics · mapped topic

• G11C11/412

  Physics · mapped topic