Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)

Patent metadata

Field	Value
Publication number	US-9105340-B2
Application number	US-201314027503-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Mar 2, 2009
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

First claim

What is claimed is:

1. An apparatus comprising:
a magnetic tunnel junction (MTJ) structure including:
a free layer;
an antiferromagnetic layer; and
a pinned layer positioned between the free layer and the antiferromagnetic layer, wherein the pinned layer is distinct from the antiferromagnetic layer, and wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic…

Assignees

• Qualcomm Inc

Inventors

• Lee Kangho
• Kang Seung H
• Zhu Xiachun

Classifications

• G11C11/1675

  Physics · mapped topic

• G11C11/16 Primary

  Physics · mapped topic

• G11C11/161

  Physics · mapped topic

• G06F30/39

  Physics · mapped topic

• H01L43/02

  Electricity · mapped topic