Methods of driving a memory

Patent metadata

Field	Value
Publication number	US-9105339-B2
Application number	US-201313799554-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	May 14, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased.

First claim

What is claimed is:

1. A method of driving a memory device, the method comprising:
erasing a plurality of memory cells of the memory device wherein each of the memory cells comprises a plurality of writable voltage distributions, and wherein the memory cells are erased using an erase pulse having a pulse time that is selected to erase less than all of the writable voltage distributions;
checking whether the memory cells have been erased;
determining that more than a predetermined percentage of the memory cells but less than all of the memory cells were erased; and
programming data into the memory cells of the memory device without performing an intervening erase operation on the plurality of memory cells in response to the determination that more than the predetermined percentage of the memory cells but less than all of the memory cells were erased.

2. The method of claim 1 , wherein the memory cells are divided into a plurality of memory blocks, and wherein programming the data into the memory cells comprises writing the data to the memory cells in response to leveling between the memory blocks.

3. The method of claim 1 , wherein each of the memory cells comprises K writable voltage distributions, and wherein programming the data into the memory cells comprises performing a first program operation using M voltage distributions among the K writable voltage distributions and performing a second program operation using (K−M) voltage distributions, wherein K is a natural number equal to or greater than three, and M is a natural number smaller than K.

4. The method of claim 1 , wherein programming the data into the memory cells comprises comparing original data to be written to the memory cells with data pre-stored in the memory cells and writing the original data to the memory cells or writing inverted data of the original data to the memory cells based on the comparison result.

5. The method of claim 4 , wherein a first number of matches between the original data and the pre-stored data and a second number of matches between the inverted data and the pre-stored data are compared, and the inverted data is written to the memory blocks if the second number is greater than the first number.

6. The method of claim 4 , further comprising writing to the memory cells at least one additional bit which indicates whether data written to the memory cells is the original data or the inverted data.

7. The method of claim 1 , wherein the memory cells are flash memory cells, wherein erasing the memory cells comprises erasing the memory cells on a memory block-by-memory block basis, and wherein the predetermined percentage of the memory cells comprises a predetermined number of memory cells in each of the memory blocks.

8. The method of claim 1 , further comprising reading data from un-erased memory cells and correcting the read data.

9. The method of claim 1 , wherein the predetermined percentage is programmed into the memory device after its manufacture.

10. A method of driving a memory device having a plurality of permissible programmed voltage distribution levels, the method comprising:
applying an erase voltage to erase a plurality of memory cells of the memory device, wherein the erase voltage has a pulse time and/or a voltage level that is selected to erase upper voltage distribution levels of the plurality of permissible programmed voltage distribution levels but not to erase lower voltage distribution levels of the plurality of permissible programmed voltage distribution levels; and
programming data into the upper voltage distribution levels of the memory cells after applying the erase voltage.

11. The method of claim 10 , further comprising programming data into the memory cells of the memory device.

12. The method of claim 11 , wherein the memory cells are divided into a plurality of memory blocks, and wherein programming the data into the memory cells comprises writing the data to the memory cells in response to leveling between the memory blocks.

13. The method of claim 11 , wherein each of the memory cells comprises K writable voltage distributions, and wherein programming the data into the memory cells comprises performing a first program operation using M voltage distributions among the K writable voltage distributions and performing a second program operation using (K−M) voltage distributions, wherein K is a natural number equal to or greater than three, and M is a natural number smaller than K.

14. The method of claim 12 , wherein programming the data into the memory cells comprises comparing original data to be written to the memory cells with data pre-stored in the memory cells and writing the original data to the memory cells or writing inverted data of the original data to the memory cells based on the comparison result.

15. A method of driving a memory device, the method Comprising:
applying an erase voltage to erase a plurality of memory cells of the memory device, each of the plurality of memory cells having a plurality of permissible programmed voltage distribution levels, wherein the erase voltage has a pulse time and/or a voltage level that is selected to erase less than all of the plurality of permissible programmed voltage distribution levels of the memory cells;
programming data into the plurality of memory cells; and
correcting errors in the data programmed into the plurality of memory cells using an error correcting code;
wherein programming the data into the memory cells comprises comparing original data to be written to the memory cells with data pre-stored in the memory cells and writing the original data to the memory cells or writing inverted data of the original data to the memory cells based on the comparison result.

16. The method of claim 15 , wherein a first number of matches between the original data and the pre-stored data and a second number of matches between the inverted data and the pre-stored data are compared, and the inverted data is written to the memory blocks if the second number is greater than the first number.

17. The method of claim 15 , further comprising writing to the memory cells at least one additional bit which indicates whether data written to the memory cells is the original data or the inverted data,

18. The method of claim 15 , wherein each of the memory cells comprises K writable voltage distributions, and wherein programming the data into the memory cells comprises performing a first program operation using M voltage distributions among the K writable voltage distributions and performing a second program operation using (K−M) voltage distributions, wherein K is a natural number equal to or greater than three, and M is a natural number smaller than K.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Twitto Moshe
• Kong Jun-Jin

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title