Memory controller using a data strobe signal and method of calibrating data strobe signal in a memory controller

US9105327B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105327-B2
Application numberUS-201313861641-A
CountryUS
Kind codeB2
Filing dateApr 12, 2013
Priority dateApr 12, 2013
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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Abstract

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A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted. The memory controller performs a training process to determine a timing offset for the data strobe gating signal with respect to said logical data strobe signal, wherein the training process provides a first phase in which the hysteresis circuitry is active and a second phase in which the hysteresis circuitry is inactive.

First claim

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We claim: 1. A memory controller comprising: input circuitry configured to receive a differential pair of data strobe signals from a memory, said input circuitry configured to generate a logical data strobe signal in dependence on a voltage difference between said differential pair of data strobe signals; hysteresis circuitry configured, when switched to an active state, to increase by a predetermined offset a threshold voltage difference at which said input circuitry is configu…

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What does patent US9105327B2 cover?
A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset …
Who is the assignee on this patent?
Advanced Risc Mach Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/1689. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).