Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US9105327B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105327-B2 |
| Application number | US-201313861641-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 12, 2013 |
| Priority date | Apr 12, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted. The memory controller performs a training process to determine a timing offset for the data strobe gating signal with respect to said logical data strobe signal, wherein the training process provides a first phase in which the hysteresis circuitry is active and a second phase in which the hysteresis circuitry is inactive.
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We claim: 1. A memory controller comprising: input circuitry configured to receive a differential pair of data strobe signals from a memory, said input circuitry configured to generate a logical data strobe signal in dependence on a voltage difference between said differential pair of data strobe signals; hysteresis circuitry configured, when switched to an active state, to increase by a predetermined offset a threshold voltage difference at which said input circuitry is configu…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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