Multiport memory architecture

Patent metadata

Field	Value
Publication number	US-9105319-B2
Application number	US-201414230555-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 13, 2003
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.

First claim

The invention claimed is:

1. A method comprising:
receiving, at one of a plurality of port buffers, serial data directly from one of a plurality of data ports;
converting, via the port buffer and at a first frequency, the serial data received directly from the data port to n-bit-wide words of parallel data;
buffering a k-word-long block of the n-bit-wide words of parallel data into a line of the port buffer as k*n bits of data by sequentially writing k words of the n-bit-wide…

Assignees

• Marvell World Trade Ltd

Inventors

• Lee Winston
• Sutardja Sehat
• Pannell Donald

Classifications

• G11C7/1075 Primary

  Physics · mapped topic