Pre-decoder circuitry
US-2024321327-A1 · Sep 26, 2024 · US
Controlling the voltage level on the word line to maintain performance and reduce access disturbs
US9105315B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105315-B2 |
| Application number | US-201213555255-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 23, 2012 |
| Priority date | Jul 23, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor memory storage device for storing data including: a plurality of storage cells, each storage cell including an access control device configured to provide the storage cell with access to or isolation from a data access port in response to an access control signal. Access control circuitry includes: access switching circuitry configured to connect a selected access control line to a voltage source; and feedback circuitry configured to feedback a change in voltage on the access control line to the access switching circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line in response to the feedback circuitry providing a feedback signal indicating that the access control line voltage has attained a predetermined value.
First claim
Opening claim text (preview).
We claim: 1. A semiconductor memory storage device for storing data comprising: a plurality of storage cells for storing said data each storage cell comprising an access control device configured to provide said storage cell with access to or isolation from a data access port in response to an access control signal; access control circuitry configured to transmit said access control signal along one of a plurality of access control lines to control a plurality of said access con…
Assignees
Inventors
Classifications
- G11C8/08Primary
Physics · mapped topic
Physics · mapped topic
- G11C11/419Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9105315B2 cover?
- A semiconductor memory storage device for storing data including: a plurality of storage cells, each storage cell including an access control device configured to provide the storage cell with access to or isolation from a data access port in response to an access control signal. Access control circuitry includes: access switching circuitry configured to connect a selected access control line t…
- Who is the assignee on this patent?
- Hold Betina, Charafeddine Kenza, Laplanche Yves Thomas, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G11C8/08. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).