Pre-decoder circuitry
US-2024321327-A1 · Sep 26, 2024 · US
Program-disturb decoupling for adjacent wordlines of a memory device
US9105314B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105314-B2 |
| Application number | US-201213457799-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 27, 2012 |
| Priority date | Apr 27, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.
First claim
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What is claimed is: 1. A method comprising: selecting two adjacent wordlines of a memory cell array; arranging program bits to be written to said memory cell array into a buffer so as to write said bits to both of said two adjacent wordlines, said program bits comprising zero-bits and one-bits; and writing said one-bits to both of said two adjacent wordlines before writing said zero-bits to both of said two adjacent wordlines. 2. The method of claim 1 ,…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9105314B2 cover?
- Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.
- Who is the assignee on this patent?
- Bedeschi Ferdinando, Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C8/08. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).