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Data processing device and a secure memory device including the same
US9104890B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104890-B2 |
| Application number | US-201313938610-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 10, 2013 |
| Priority date | Jul 12, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A data processing device includes a first register unit, a second register unit and a data handling unit. The first register unit generates an address signal based on a first control signal. The address signal points to a region in an external storage device where first data is stored. The second register unit receives the first data output from the external storage device, generates second data based on the first data and a second control signal, and selectively generates a detectable error in the second data according to an operating mode when a fault is injected into the first data. A bit number of the detectable error in the second data is larger than a bit number of the fault injected into the first data. The data handling unit selectively processes the second data depending on whether the detectable error is generated.
First claim
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What is claimed is: 1. A data processing device, comprising: a first register circuit configured to generate an address signal based on a first control signal, wherein the address signal points to a region in an external storage device where first data is stored; a second register circuit configured to receive the first data output from the external storage device, generate second data based on the first data and a second control signal, and selectively generate a detectable err…
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- What does patent US9104890B2 cover?
- A data processing device includes a first register unit, a second register unit and a data handling unit. The first register unit generates an address signal based on a first control signal. The address signal points to a region in an external storage device where first data is stored. The second register unit receives the first data output from the external storage device, generates second dat…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F21/64. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).