Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
Method and system for automatic generation of processor datapaths
US9104827B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104827-B2 |
| Application number | US-201213430629-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 26, 2012 |
| Priority date | Dec 19, 2005 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.
First claim
Opening claim text (preview).
What is claimed is: 1. A computer-implemented method for automatically generating a plurality of shared datapaths, comprising: receiving a behavior description for each of a set of operations; automatically generating the plurality of shared datapaths from a plurality of seed datapaths to implement behavior of the set of operations; and identifying common hardware resources of the plurality of shared datapaths, wherein certain datapaths of the plurality of shared datapaths are…
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Physics · mapped topic
- G06F30/327Primary
Physics · mapped topic
Physics · mapped topic
- G06F17/505Primary
Physics · mapped topic
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- What does patent US9104827B2 cover?
- Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The …
- Who is the assignee on this patent?
- Petkov Darin Stamenov, Goodwin David William, Maydan Dror Eliezer, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F30/327. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).