Technologies for dividing work across accelerator devices
US-2024143410-A1 · May 2, 2024 · US
Multi-master bus architecture for system-on-chip
US9104819B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104819-B2 |
| Application number | US-201013509945-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 16, 2010 |
| Priority date | Nov 18, 2009 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A system on chip and associated method facilitates transfer of data between two or more master blocks through a bus on chip. The system creates a direct path for data transferring from a master port of a bus to another master port of the same bus. The bus includes a plurality of signals used to transfer data, address or control information between two or several blocks on chip. The behavior of bus connector block is controlled according to the destination of data coming from a master port. The system includes a master-connector-slave arrangement that enables the direct data communication between two or several master blocks, without taking any slave blocks as the data buffer. A bus connector block is configured to manage bus arbitrating and address decoding, and particularly to create the direct data path between master blocks.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for facilitating transfer of data between two components through a bus on chip, comprising: a) selectively creating a data path for data transferring between a first master port of a bus and a second master port of the same bus in undivided bus transactions, wherein data transferred between the first and second master ports is not stored in a slave device; and b) controlling connectivity in a bus connector block to selectively create the data path…
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Physics · mapped topic
- G06F13/4022Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104819B2 cover?
- A system on chip and associated method facilitates transfer of data between two or more master blocks through a bus on chip. The system creates a direct path for data transferring from a master port of a bus to another master port of the same bus. The bus includes a plurality of signals used to transfer data, address or control information between two or several blocks on chip. The behavior of …
- Who is the assignee on this patent?
- Huang Bobby, St Ericsson Sa
- What technology area does this patent fall under?
- Primary CPC classification G06F13/4022. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).