Processor, multiprocessor system, and method for causing memory managing apparatus to manage shared memory

US9104636B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9104636-B2
Application numberUS-201113027482-A
CountryUS
Kind codeB2
Filing dateFeb 15, 2011
Priority dateOct 26, 2010
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each processor and subtracts 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated. The releaser releases the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0.

First claim

Opening claim text (preview).

The invention claimed is: 1. A processor sharing a shared memory shared by a plurality of processors, the shared memory comprising an allocation memory block and a management memory block, the processor comprising: an allocator configured to secure a memory area in the shared memory allocated to each of the processors based on a request of each of the processors, and register a plurality of reference counters corresponding one-to-one to the processors; an updater configured to a…

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What does patent US9104636B2 cover?
A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to th…
Who is the assignee on this patent?
Nonogaki Nobuhiro, Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification G06F15/167. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).