Memory timing optimization using pattern based signaling modulation

Patent metadata

Field	Value
Publication number	US-9104635-B2
Application number	US-201113993010-A
Country	US
Kind code	B2
Filing date	Dec 28, 2011
Priority date	Dec 28, 2011
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load.

First claim

What is claimed is:

1. A method comprising:
determining, via a processor, a worst-case setup and hold time based on both a first load and a second load on a bus, wherein the worst-case setup and hold time is associated with (i) an amount of time a data signal is to be held steady before a clock event and (ii) an amount of time the data signal is to be held steady after the clock event, wherein the worst-case setup and hold time is further based on data stored in a BIOS;
determin…

Assignees

• Uduebho Oseghale O
• Norman Adam J
• Intel Corp

Inventors

• Uduebho Oseghale O
• Norman Adam J

Classifications

• G06F13/1689

  Physics · mapped topic

• G11C29/028

  Physics · mapped topic

• G11C29/023 Primary

  Physics · mapped topic

• G06F13/161 Primary

  Physics · mapped topic