Decoder, decoding method, memory controller, and memory system
US-2024429941-A1 · Dec 26, 2024 · US
Memory system
US9104596B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104596-B2 |
| Application number | US-201314017259-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 3, 2013 |
| Priority date | Jan 8, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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According to one embodiment, a memory device includes a memory unit including a first subunit and a second subunit, a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data, and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit. The control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory device comprising: a memory unit including a first subunit and a second subunit; a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data; and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit, whe…
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- G06F11/1048Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104596B2 cover?
- According to one embodiment, a memory device includes a memory unit including a first subunit and a second subunit, a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data, and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the sec…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1048. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).