Address Range Based Memory Hints for Prefetcher, Cache and Memory Controller
US-2024385966-A1 · Nov 21, 2024 · US
US9104593B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104593-B2 |
| Application number | US-201213714466-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 14, 2012 |
| Priority date | Dec 14, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB. Some embodiments of the method also include filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB.
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What is claimed: 1. A method, comprising: receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB; and filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB; posting the request to the second TLB in response…
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