Dynamically sized redundant write buffer with sector-based tracking
US-2024143511-A1 · May 2, 2024 · US
eDRAM refresh in a high performance cache architecture
US9104581B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104581-B2 |
| Application number | US-82224510-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 24, 2010 |
| Priority date | Jun 24, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.
First claim
Opening claim text (preview).
The invention claimed is: 1. A computer system for implementing cache memory refreshes in a high performance cache comprising: a cache comprising a memory refresh requestor, a memory request interpreter, a cache memory, a cache pipeline, and a cache controller on a single chip, the cache pipeline configured to receive a memory refresh request to refresh contents of a memory address range in the cache memory and a memory access request for the memory address range; the cache cont…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9104581B2 cover?
- A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request inte…
- Who is the assignee on this patent?
- Fee Michael, O'Neill Jr Arthur J, Sonnelitter Iii Robert J, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0893. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).