Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation
US-9213563-B2 · Dec 15, 2015 · US
Optimizing memory bandwidth consumption using data splitting with software caching
US9104577B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104577-B2 |
| Application number | US-201314010984-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 27, 2013 |
| Priority date | Aug 27, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
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A computer processor collects information for a dominant data access loop and reference code patterns based on data reference pattern analysis, and for pointer aliasing and data shape based on pointer escape analysis. The computer processor selects a candidate array for data splitting wherein the candidate array is referenced by a dominant data access loop. The computer processor determines a data splitting mode by which to split the data of the candidate array, based on the reference code patterns, the pointer aliasing, and the data shape information, and splits the data into two or more split arrays. The computer processor creates a software cache that includes a portion of the data of the two or more split arrays in a transposed format, and maintains the portion of the transposed data within the software cache and consults the software cache during an access of the split arrays.
First claim
Opening claim text (preview).
What is claimed is: 1. A computer program product for data splitting of an array using a software cache, the computer program product comprising: one or more non-transitory computer-readable storage medium(s) and program instructions stored on the one or more non-transitory computer-readable storage medium(s), the program instructions comprising: program instructions to collect information for a dominant data access loop and reference code patterns based on data reference patter…
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Classifications
- G06F8/4442Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/0837Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104577B2 cover?
- A computer processor collects information for a dominant data access loop and reference code patterns based on data reference pattern analysis, and for pointer aliasing and data shape based on pointer escape analysis. The computer processor selects a candidate array for data splitting wherein the candidate array is referenced by a dominant data access loop. The computer processor determines a d…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification G06F8/4442. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).