Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Wear leveling for a memory device
US9104547B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104547-B2 |
| Application number | US-201113197460-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 3, 2011 |
| Priority date | Aug 3, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of operating a memory device having an array of memory cells arranged in a plurality of blocks, the method comprising: receiving a write command comprising information identifying a particular group of one or more blocks of the plurality of blocks to be excluded from wear leveling operations and having associated data to be stored to the particular group of one or more blocks; storing the information identifying the particular group of one or mor…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/0246Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104547B2 cover?
- Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected …
- Who is the assignee on this patent?
- Baltar Robert, Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).