Binary array with LSB dithering in a closed loop system
US-9501261-B2 · Nov 22, 2016 · US
Floating-point error detection and correction
US9104515B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104515-B2 |
| Application number | US-201213715707-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 14, 2012 |
| Priority date | Dec 14, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first operand to a first comparison register. The method may also include copying a second exponent of the second operand to a second comparison register. The method may further include comparing the first exponent in the first comparison register to the second exponent in the second comparison register. Based on the comparison, a determination may be made whether the instruction includes a potential floating-point error when executing the instruction using the first operand and the second operand formatted according to a first precision.
First claim
Opening claim text (preview).
What is claimed is: 1. A non-transitory computer readable media including computer executable instructions configured to cause a processing device to perform operations to correct potential floating-point errors in an addition or a subtraction calculation, the operations comprising: receiving a first subset of a plurality of instructions within an original program, the first subset including a first instruction; for the first instruction, copying a first exponent of a first oper…
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Frequently asked questions
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- What does patent US9104515B2 cover?
- An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first …
- Who is the assignee on this patent?
- Fujitsu Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F7/485. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).