Information processing apparatus
US-2024385843-A1 · Nov 21, 2024 · US
Processor architecture for processing variable length instruction words
US9104426B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104426-B2 |
| Application number | US-98197307-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 1, 2007 |
| Priority date | Dec 3, 2004 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimized for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.
First claim
Opening claim text (preview).
The invention claimed is: 1. A processor comprising: a plurality of registers to store data; an instruction decoder to decode a first instruction word that is to include a first plurality of at least three instructions, wherein the first instruction word is part of an instruction set architecture having instruction words with a variable instruction length; and at least three groups of execution units coupled with the instruction decoder and the plurality of registers, wherei…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F9/3885Primary
Physics · mapped topic
- G06F9/38Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104426B2 cover?
- A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimized for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place signific…
- Who is the assignee on this patent?
- Duller Andrew, Panesar Gajinder Singh, Claydon Peter, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3885. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).