Self-healing using an alternate boot partition
US-2015378746-A1 · Dec 31, 2015 · US
Method of operating a video decoding system
US9104424B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104424-B2 |
| Application number | US-201113205776-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 9, 2011 |
| Priority date | Apr 1, 2002 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of decoding an encoded digital data stream, comprising: (a) executing a first stage comprising: (i) performing a first decoding function on an n th data element of the data stream; and (ii) performing at least a portion of a second decoding function on an n+1 st data element of the data stream within a time during which the first decoding function is performed on the n th data element; and (b) when the first function is completed with resp…
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Electricity · mapped topic
Electricity · mapped topic
- G06F9/3861Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9104424B2 cover?
- A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the da…
- Who is the assignee on this patent?
- Alvarez Jose R, Macinnis Alexander G, Zhong Sheng, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3861. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).