Processor with hardware supported memory buffer overflow detection
US-11868774-B2 · Jan 9, 2024 · US
Data processing system having selective redundancy and method therefor
US9104403B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104403-B2 |
| Application number | US-85859910-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 18, 2010 |
| Priority date | Aug 18, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction; when…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F9/30145Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104403B2 cover?
- A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the s…
- Who is the assignee on this patent?
- Morrison Gary R, Moyer William C, Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30145. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).