Rate controlled first in first out (FIFO) queues for clock domain crossing

Patent metadata

Field	Value
Publication number	US-9104345-B2
Application number	US-201414211805-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Dec 1, 2010
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues.

First claim

What is claimed is:

1. A system comprising:
a memory; and
one or more processors to:
detect a read operation of an asynchronous first in, first out (FIFO) queue;
increment a credit counter based on the read operation;
determine that a count value of the credit counter satisfies a threshold value;
generate a write pulse signal to perform a write operation to the asynchronous FIFO queue based on the count value satisfying the threshold value;
smooth the write pulse signal…

Assignees

• Juniper Networks Inc

Inventors

• Agrawal Anurag
• Thomas Philip A

Classifications

• G06F1/04 Primary

  Physics · mapped topic

• G06F5/12 Primary

  Physics · mapped topic