Display device and manufacturing method thereof

US9104073B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9104073-B2
Application numberUS-201314034827-A
CountryUS
Kind codeB2
Filing dateSep 24, 2013
Priority dateOct 1, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a display device having high reliability, even if being a narrow framing type, and a method for manufacturing thereof, having a display panel, being made up with a first substrate 101 and a second substrate 201 , which are adhered with using a seal 301 , a main SOC 302 is disposed like a wall, on a peripheral end portion of the first substrate 101 and the second substrate 201 , and the seal 301 is disposed inwardly of the main SOC 302 . Also, in a method for manufacturing thereof, the main SOC 302 is formed in a region including a cutting plane between the display panel regions neighboring with, and on the cutting plane is made the cutting thereof.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a display device, comprising the following steps of: a step for preparing a first substrate having plural numbers of display panel regions, each having an effective display region; a step for forming a first organic film covering over the plural numbers of display panel regions on the first substrate; a step for preparing a second substrate, having plural numbers of display panel regions, each having an effective display region, and being formed with a main SOC for use of adjusting a gap distance in a region including a cutting plane of the display panel region; a step for forming a second organic film covering over the plural numbers of display panel regions on the second substrate; a step for applying a seal on a region of the second substrate, including a region where the main SOC is formed and/or a region including a cutting plane of the display panel region of the first substrate; a step for laminating the first substrate and the second substrate, so that the first organic film of the first substrate faces to the second organic film of the second substrate, and thereby adhering those to each other by the seal; and a step for cutting out the display panel region on the cutting plane, so that the main SOC is separated. 2. The method for manufacturing a display device according to claim 1 , wherein plural numbers of sub SOCs having height lower than that of the main SOC are disposed in an inside of the seal, on the second substrate. 3. The method for manufacturing a display device according to claim 1 , wherein the first substrate has an inorganic passivation film, and an upper layer passivation film or an organic passivation film, which is formed on the inorganic passivation film, and the upper layer passivation film or the organic passivation film has plural numbers of grooves within a region where the seal is formed. 4. The method for manufacturing a display device according to claim 1 , wherein the first substrate has an inorganic passivation film, and an upper layer passivation film or an organic passivation film, which is formed on the inorganic passivation film, the upper layer passivation film or the organic passivation film has plural numbers of grooves within a region where the seal is formed, plural numbers of sub SOCs having height lower than that of the main SOC are formed in an side of the seal on the second substrate, and the sub SOCs and the grooves are disposed so as to overlap each other when viewed from vertically above. 5. The method for manufacturing a display device according to claim 4 , wherein the first substrate has a gate wiring and a drain wiring, and both the gate wiring and the drain wiring are disposed not to overlap on the sub SOCs and the grooves when viewed from vertically above. 6. The method for manufacturing a display device according to claim 1 , wherein the first substrate has an inorganic passivation film, and the inorganic passivation film has plural numbers of grooves within a region where the seal is formed. 7. The method for manufacturing a display device according to claim 1 , wherein the first substrate has an inorganic passivation film, the inorganic passivation film has plural numbers of grooves within a region where the seal is formed, plural numbers of sub SOCs having height lower than that of the main SOC are disposed within an inside of the seal on the second substrate, and the sub SOCs and the grooves are disposed so as to overlap each other when viewed from vertically above. 8. The method for manufacturing a display device according to claim 7 , wherein the first substrate has a gate wiring and a drain wiring, and both the gate wiring and the drain wiring are disposed not overlap on the sub SOCs and the grooves when viewed from vertically above. 9. The method for manufacturing a display device according to claim 1 , wherein the display panel has an effective display region, comprising SOC for defining a gap distance between the first substrate and the second substrate, and height of the main SOC is higher than height of the SOC in the effective display region. 10. The method for manufacturing a display device according to claim 9 , wherein the main SOC and the SOC in the effective display region are formed in the same step.

Assignees

Inventors

Classifications

  • spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

  • Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

  • Protective arrangements · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

  • Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title

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Frequently asked questions

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What does patent US9104073B2 cover?
In a display device having high reliability, even if being a narrow framing type, and a method for manufacturing thereof, having a display panel, being made up with a first substrate 101 and a second substrate 201 , which are adhered with using a seal 301 , a main SOC 302 is disposed like a wall, on a peripheral end portion of the first substrate 101 and the second substrate 201 , and …
Who is the assignee on this patent?
Japan Display Inc
What technology area does this patent fall under?
Primary CPC classification G02F1/13454. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).