Interposer instrumentation method and apparatus
US-2024133947-A1 · Apr 25, 2024 · US
US9103885B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9103885-B2 |
| Application number | US-201414494092-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 23, 2014 |
| Priority date | Nov 28, 2001 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Official abstract text for this publication.
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising: A. input pads and output pads; B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second output pad; C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first outpu…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Physics · mapped topic
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