Integrated circuit with plural comparators receiving expected data and mask data from different pads

US9103885B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9103885-B2
Application numberUS-201414494092-A
CountryUS
Kind codeB2
Filing dateSep 23, 2014
Priority dateNov 28, 2001
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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Abstract

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Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit comprising: A. input pads and output pads; B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second output pad; C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first outpu…

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What does patent US9103885B2 cover?
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester trans…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification G01R31/318536. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).