Circuit And Method For Monolithic Stacked Integrated Circuit Testing
US-2015355277-A1 · Dec 10, 2015 · US
Method for scan testing three-dimensional chip
US9103878B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9103878-B2 |
| Application number | US-201314394296-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 17, 2013 |
| Priority date | Apr 17, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method for scan testing a three-dimensional chip, comprising: establishing a scan forest structure for the three-dimensional chip; generating a first test set and a plurality of test periods, and dividing the first test set into a plurality of test subsets; distributing test vectors in the plurality of test subsets into the plurality of test periods; obtaining a current hotspot of the three-dimensional chip; ranking the plurality of test subsets in accordance with an order of temperature rising values from small to large to obtain a test vector strategy; selecting the test subsets corresponding to the temperature rising values less than a temperature threshold from the plurality of test subsets according to the test vector strategy, so as to generate a second test set; and applying the second test set to the scan forest structure, and updating the current hotspot of the three-dimensional chip.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for scan testing a three-dimensional chip, comprising steps of: establishing a scan forest structure for the three-dimensional chip, wherein the scan forest structure comprises a plurality of scan input ports and a plurality of scan tree structures corresponding to the plurality of scan input ports, each of the plurality of scan tree structures comprises a plurality of scan chains, and scan triggers in a same scan chain have different successors;…
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Physics · mapped topic
- G01R31/318513Primary
Physics · mapped topic
- G01R31/3173Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9103878B2 cover?
- A method for scan testing a three-dimensional chip, comprising: establishing a scan forest structure for the three-dimensional chip; generating a first test set and a plurality of test periods, and dividing the first test set into a plurality of test subsets; distributing test vectors in the plurality of test subsets into the plurality of test periods; obtaining a current hotspot of the three-d…
- Who is the assignee on this patent?
- Univ Tsinghua
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318513. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).