Selective voltage binning leakage screen
US-9772374-B2 · Sep 26, 2017 · US
Apparatus and method for IDDQ tests
US9103877B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9103877-B2 |
| Application number | US-201213438745-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 3, 2012 |
| Priority date | Apr 3, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method for conducting IDDQ tests for a device having a plurality of test sites is disclosed. The method includes identifying voltage ranges for each of the plurality of test sites, closing a switch in each of a plurality of voltage drop setup circuits, and setting each of the plurality of test sites to one of a plurality of logic states. Each of the plurality of voltage drop setup circuits includes a resistor parallelly coupled to the switch. One terminal of each voltage drop setup circuit is coupled to a voltage source and the other terminal of each voltage drop setup circuit is coupled to respective tester channels of each of the plurality of test sites. After opening the switch in each of the plurality of voltage drop setup circuits, the voltage drop across the resistor in each voltage drop setup circuit is measured.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for conducting IDDQ tests for a plurality of devices under test (DUTs) having a plurality of test sites, each DUT having a test site, comprising: (a) identifying voltage ranges for each of the plurality of test sites; (b) closing a switch in each of a plurality of voltage drop setup circuits, wherein each of the plurality of voltage drop setup circuits includes a resistor parallelly connected to the switch, and a first terminal of each of the plur…
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- G01R31/3008Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9103877B2 cover?
- A method for conducting IDDQ tests for a device having a plurality of test sites is disclosed. The method includes identifying voltage ranges for each of the plurality of test sites, closing a switch in each of a plurality of voltage drop setup circuits, and setting each of the plurality of test sites to one of a plurality of logic states. Each of the plurality of voltage drop setup circuits in…
- Who is the assignee on this patent?
- Studnicki Richard, Sandisk Technologies Inc
- What technology area does this patent fall under?
- Primary CPC classification G01R31/3008. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).