Method of ONO integration into logic CMOS flow

US9102522B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9102522-B2
Application numberUS-201213434347-A
CountryUS
Kind codeB2
Filing dateMar 29, 2012
Priority dateApr 24, 2009
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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Abstract

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An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

First claim

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What is claimed is: 1. A method comprising: forming above a surface on a substrate a stack of gate layers including at least two dielectric layers separated by at least one gate layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; sequentially forming on sidewalls of the first opening a blocking diele…

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What does patent US9102522B2 cover?
An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a sour…
Who is the assignee on this patent?
Ramkumar Krishnaswamy, Jin Bo, Jenne Fredrick, and 1 more
What technology area does this patent fall under?
Primary CPC classification B82Y10/00. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).