Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
US9102522B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9102522-B2 |
| Application number | US-201213434347-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 29, 2012 |
| Priority date | Apr 24, 2009 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Official abstract text for this publication.
An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
Opening claim text (preview).
What is claimed is: 1. A method comprising: forming above a surface on a substrate a stack of gate layers including at least two dielectric layers separated by at least one gate layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; sequentially forming on sidewalls of the first opening a blocking diele…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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