Stacked inorganic-organic dielectrics for thin film capacitors in package substrates
US-2024222295-A1 · Jul 4, 2024 · US
Method for manufacturing multilayer printed wiring board
US9101070B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9101070-B2 |
| Application number | US-201113185295-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 18, 2011 |
| Priority date | Apr 18, 2007 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
Official abstract text for this publication.
A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second electrode configured to be charged by a positive charge. A dielectric layer is interposed between the first electrode and second electrode, and an ionization tendency of the first metal is larger than and ionization tendency of the second metal.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for manufacturing a multilayer printed wiring board, comprising: providing a core substrate; laminating a resin insulation layer on the core substrate; forming a capacitor section including a high- K dielectric sheet and being coupled to the resin insulation layer by: providing a first electrode comprising a first metal, providing a second electrode opposing the first electrode, the second electrode comprising a second metal having a s…
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Electricity · mapped topic
- H05K1/162Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9101070B2 cover?
- A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second…
- Who is the assignee on this patent?
- Tanaka Hironori, Shimizu Keisuke, Ibiden Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H05K1/162. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).