Semiconductor device
US-2016307607-A1 · Oct 20, 2016 · US
Circuit for reverse biasing inverters for reducing the power consumption of an SRAM memory
US9099993B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099993-B2 |
| Application number | US-201214356562-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 18, 2012 |
| Priority date | Nov 7, 2011 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
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CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.
First claim
Opening claim text (preview).
The invention claimed is: 1. A bias circuit for inverters of an integrated circuit, each inverter comprising an NMOS transistor and a PMOS transistor powered by a power supply voltage Varray, with means for applying a first rear bias voltage NBIAS to wells of the NMOS transistors and a second rear bias voltage PBIAS to wells of the PMOS transistors, the bias circuit supplying the bias voltages and comprising: a detection array comprising a set of many inverters mounted in parallel…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9099993B2 cover?
- CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: …
- Who is the assignee on this patent?
- Commissariat Energie Atomique
- What technology area does this patent fall under?
- Primary CPC classification G11C5/146. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).