Image sensor with a curved surface

US9099604B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9099604-B2
Application numberUS-201313858481-A
CountryUS
Kind codeB2
Filing dateApr 8, 2013
Priority dateApr 13, 2012
Publication dateAug 4, 2015
Grant dateAug 4, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing an image sensor, comprising the successive steps of: defining, in a semiconductor substrate extending on a semiconductor support with an interposed insulating layer, through trenches delimiting columns, each column having a distal end and a proximal end separate from the distal end; forming one or more pixels in the distal end of each of the columns; and deforming a structure so that the proximal ends of each of said columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap, wherein the proximal end of each column includes the semiconductor substrate without pixels. 2. The method of claim 1 , wherein each of the columns has an upper surface having a dimension that is smaller than 10 μm. 3. The method of claim 1 , further comprising, after the defining through trenches, filling the through trenches with an insulating material. 4. The method of claim 3 , further comprising, before deforming the structure, removing the insulating material. 5. The method of claim 4 , wherein removing the insulating material is followed by filling of the through trenches with a material. 6. The method of claim 1 , further comprising, after defining through trenches delimiting columns, forming an interconnection stack over the distal end of the columns. 7. The method of claim 6 , further comprising, after the step of forming an interconnection stack, forming a layer over the interconnection stack and removing the semiconductor support and the insulating layer. 8. The method of claim 7 , wherein prior to forming the layer over the interconnection stack, forming, on the interconnection stack, a layer of a deformable material. 9. The method of claim 7 , wherein prior to forming the layer over the interconnection stack, etching of a cavity at a surface of the layer, said cavity being defined and positioned to coincide, at the installation, with the entire surface defined by the columns. 10. The method of claim 1 , wherein defining through trenches delimiting columns is followed by a column wall restoring step. 11. The method of claim 1 , wherein defining through trenches delimiting columns comprises at least one of plasma etching, pulsed plasma etching, and reactive ion etching. 12. A method for manufacturing a semiconductor device, the method comprising: forming through trenches on a first side of a first semiconductor substrate; forming at least one pixel on a second side of the first semiconductor substrate, wherein the second side is a distal end and opposite to and spaced apart from the first side; placing a semiconductor support on the second side of the first semiconductor substrate with an insulating layer between the first semiconductor substrate and the semiconductor support; positioning the first semiconductor substrate on a surface, wherein the first side of the first semiconductor substrate is the side closest to the surface; and deforming the first semiconductor substrate, wherein the first side of the first semiconductor substrate includes semiconductor material and does not include one or more pixels. 13. The method of claim 12 , wherein the act of forming through trenches creates columns on the first side of the first semiconductor substrate. 14. The method of claim 13 , further comprising: restoring the walls of the columns. 15. The method of claim 13 , wherein the columns have a dimension smaller than 10 μm. 16. The method of claim 12 , wherein the through trenches are formed using at least one of plasma etching, pulsed plasma etching, or reactive ion etching. 17. The method of claim 12 , further comprising: filling the through trenches with a material. 18. The method of claim 17 , wherein the material is an insulating material. 19. The method of claim 12 , further comprising: forming at least one conductive via in the insulating layer to form an interconnection stack. 20. The method of claim 19 , further comprising: forming a layer of a deformable material on the interconnection stack. 21. The method of claim 12 , wherein the through trenches are patterned in concentric circles. 22. The method of claim 12 , wherein the through trenches are patterned in stripes. 23. The method of claim 12 , wherein the through trenches are patterned in a rosette. 24. The method of claim 12 wherein deforming the first semiconductor substrate comprises applying stress that causes the first semiconductor substrate to deform. 25. A method comprising: forming through trenches in a substrate of semiconductor material, the through trenches delimiting columns having distal first ends and second ends separated from the first ends, the substrate located on an insulating layer over a support, the substrate, the insulating layer, and the support forming a structure; filling the through trenches with an insulating material; forming a single pixel at the first end of each of the columns; removing the insulating material located in the through trenches; and deforming the structure in a manner that draws the second ends of each of the columns closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap, wherein the second ends of the columns include the semiconductor material and do not include pixels. 26. The method of claim 25 , wherein filling the through trenches comprises filling the through trenches at a first side of the substrate, and wherein removing the insulating material comprises removing the insulating material at a second side of the substrate. 27. The method of claim 25 , wherein forming through trenches includes at least one of plasma etching, pulsed plasma etching, and reactive ion etching.

Assignees

Inventors

Classifications

  • Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery · CPC title

  • H10F71/00Primary

    Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

  • H01L31/18Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9099604B2 cover?
A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
Who is the assignee on this patent?
St Microelectronics Sa, St Microelectronics Crolles 2
What technology area does this patent fall under?
Primary CPC classification H10F39/8023. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).