Static random access memory device with stacked fets
US-2024431087-A1 · Dec 26, 2024 · US
US9099490B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099490-B2 |
| Application number | US-201213631534-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 28, 2012 |
| Priority date | Sep 28, 2012 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
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What is claimed is: 1. A high electron mobility field effect transistor (HEMT), comprising: a group III-N semiconductor channel layer disposed over a substrate; a gate stack disposed over a first region of the channel layer; a source region in contact with the channel layer on a first side of the gate stack; a drain region in contact with the channel layer on a second side of the gate stack opposite the source region; a dielectric liner disposed over a first length of a se…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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