Self-aligned silicide formation on source/drain through contact via

Patent metadata

Field	Value
Publication number	US-9099474-B2
Application number	US-201213706530-A
Country	US
Kind code	B2
Filing date	Dec 6, 2012
Priority date	Mar 24, 2011
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate having a functional gate structure formed on a semiconductor substrate with a gate-last scheme that includes a first layer formed on the semiconductor substrate, a gate electrode formed on the first layer, and a second layer formed on sides of the gate electrode and on a bottom of the gate electrode;
a sidewall layer formed on the side of the first layer and the side of the second layer;
an…

Assignees

• Toshiba Kk

Inventors

• Uozumi Yoshihiro

Classifications

• H10D64/0112

  Electricity · mapped topic

• H10W20/081

  Electricity · mapped topic

• H10W20/40

  Electricity · mapped topic

• H10W20/20

  Electricity · mapped topic

• H10W20/033

  Electricity · mapped topic